1. Field of the Invention
An aspect of the present invention relates to a display data receiving circuit and a display panel driver, and more specifically, to a display data receiving circuit for receiving display data serially transferred in a display apparatus, and a display panel driver including the display data receiving circuit.
2. Description of Related Art
In a display apparatus using a liquid crystal display panel and other display panels, a data transfer method of display data (tone data) is determined according to the specifications of the display panel, specifically, the number of pixels. For example, in a display apparatus providing a display panel whose number of pixels is large such as a display panel of XGA (extended graphic array: 1024×768 pixels), because it is necessary to transfer display data at the high data transfer rate, data transfer of the display data is performed in the high clock frequency. On the other hand, in a display apparatus providing a display panel whose number of pixels is small such as a display panel of QVGA (quarter video graphic array: 320×240 pixels), data transfer of the display data is performed in the low clock frequency. Other resolutions refer to VGA (video graphic array: 640×480 pixels) and HVGA (half VGA: 480×320 pixels). Total number of pixels of XGA, VGA, HVGA, and QVGA refer to DXGA, DVGA, DHVGA, and DQVGA, respectively, and the following relation is valid:DXGA>DVGA>DHVGA>DQVGA.
Generally, the data transfer rate can be also controlled so that a transmitter-receiver circuit operates in synchronization with only one edge of a rising edge and a falling edge of a clock signal, or both edges. As known widely, DRAM (dynamic random access memory) may be configured to execute data input/output according to both of a rising edge and a falling edge of clock signal, and such DRAM is referred to as DDR-SDRAM (double data rate-synchronous dynamic random access memory). It is known that DDR-SDRAM has such an advantage that the data transfer rate of DDR-SDRAM is twice as compared with DRAM (such DRAM is referred to as SDR-SDRAM (single data rate-SDRAM)) which executes data input/output according to one of a rising edge and a falling edge of a clock signal. Japanese Patent Laid-Open No. 2000-182399 discloses DRAM which can execute both of an operation which synchronizes with only one of a rising edge and a falling edge of a clock signal, and an operation which synchronizes with both edges.
In a display apparatus, particularly, a display apparatus used for a portable device, reduction of the power consumption is one of the important problems. One approach for this problem is to change a data transfer method of display data according to the display size of a display panel. Japanese Patent Laid-Open No. 9-244587 discloses a liquid crystal display control circuit which changes a data transfer method of display data according to the display size specification of a liquid crystal display panel. Such a well-known liquid crystal display control circuit is a circuit for transmitting display data and control signals to a driver control LSI (Large scale integrated circuit) which controls a column driver and a common driver. The liquid crystal display control circuit provides three display control LSIs which can be controlled independently. Display data is supplied from each of the three display control LSIs to the driver control LSI, and control signals are supplied from one of the three display control LSIs to the driver control LSI. When the display panel (e.g. XGA display panel) whose number of pixels is large is driven, all of the three display control LSIs are used. On the other hand, one or two of the three display control LSIs are selected and used for the display panel whose number of pixels is small. Display data is supplied from the selected display control LSIs to the driver control LSI. If one or two of the three display control LSIs are selected and used, the power consumption of a liquid crystal display apparatus can be reduced in case that the display panel whose number of pixels is small is used.
Japanese Patent Laid-Open No. 10-97226 discloses another approach for reducing the power consumption of a liquid crystal display apparatus. In this liquid crystal display apparatus, a high frequency oscillating circuit which is a source of a high frequency timing signal used for transferring display data operates intermittently. Specifically, if a rewrite of display data is directed from MPU (micro processing unit), the oscillation of the high frequency oscillating circuit is started, and if transferring display data is terminated, the oscillation of the high frequency oscillating circuit is stopped. Thereby, the power consumption of a liquid crystal display apparatus is reduced.
However, in the above existing liquid crystal display apparatus, there is such a problem that the electric power consumed while display data is being received can not be reduced. In the liquid crystal display control circuit disclosed in Japanese Patent Laid-open No. 9-244587, while the power consumption of the display control LSI which transmits display data is reduced, the power consumption of the driver control LSI which receives display data is not reduced.
On the other hand, in the liquid crystal display apparatus disclosed in Japanese Patent Laid-open No. 10-97226, while the power consumption of the display panel driver while data transfer is standing by can be reduced certainly, the power consumption of the display panel driver while display data is being transferred can not be reduced.
The problem of the power consumption is particularly important when a display data receiving circuit which receives display data is designed so as to be able to change the transfer rate of display data. When the transfer rate of display data can be changed, the display data receiving circuit is required to be designed so as to be able to receive display data certainly when the transfer rate of display data is maximum. However, such a design, generally, uselessly increases the power consumption in case that the transfer rate of display data is slow.